The present invention relates generally to integrated circuit devices, and, more particularly, to a high-density bitline selection apparatus for semiconductor memory devices.
Static Random Access Memories (SRAMs) are memory elements that store data in the form of complementary low voltage and high voltage at opposite sides of the memory cell. An SRAM retains the memory value therein so long as power is applied to the circuit, unlike dynamic random access memory (DRAM) that must be periodically refreshed in order for the data to be maintained therein. Conventionally, if the “true” node of an SRAM is read as a high voltage, then the value of the SRAM cell is logical one. Conversely, if the true node is read as a low voltage, the value of the SRAM cell is logical zero.
Due to the high degree of miniaturization possible today in semiconductor technology, the size and complexity of designs that may be implemented in hardware has increased dramatically. This has made it technologically feasible and economically viable to develop high-speed, application specific architectures featuring a performance increase over previous architectures. Process scaling has been used in the miniaturization process to reduce the area needed for both logic functions and memory (such as SRAM) in an effort to lower the product costs. Process scaling continues to improve performance, but can also come at the expense of power.
Precharged Complementary Metal Oxide Semiconductor (CMOS) domino logic techniques may be applied to functional blocks to reduce power. Accordingly, domino logic forms an attractive design style for high performance designs since its low switching threshold and reduced transistor count leads to fast and area efficient circuit implementations. Thus, domino CMOS has become a prevailing logic family for many high performance CMOS applications (including SRAM devices) and is used in many state-of-the-art processors due to its high-speed capabilities. Notwithstanding such architectures, however, it is still desirable to be able to implement a memory select circuit, such as a local bitline select circuit, in a manner that utilizes fewer devices resulting in less area. This is particularly desirable for large SRAM devices, in which a local bitline select circuit is a significant pitch concern.